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application note AN4146 design guidelines for quasi-resonant converters using fscq-series fairchild power switch (fps tm ) www.fairchildsemi.com ?2005 fairchild semiconductor corporation abstract in general, a quasi-resonant converter (qrc) shows lower emi and higher power conversi on efficiency compared to the conventional hard switch ed converter with a fixed switching frequency. therefore, it is well suited for color tv applications that are noise sensitive. this application note presents practical design cons iderations of quasi-resonant converters for color tv applications employing fscq- series fps tm (fairchild power switch). it includes designing the transformer, output filter and sync network, selecting the components and cl osing the feedback loop. the step-by-step design procedure described in this application note will help engineers design quasi-resonant converter easily. to make the design process more efficient, a software design tool, fps design assistant which contains all the equations described in this application note, is also provided. the design procedure is verified through an experimental prototype converter. rev. 1.0.1 1. introduction the fscq-series fps tm (fairchild power switch) is an integrated pulse width modu lation (pwm) controller and sense fet specifically designed for quasi-resonant off-line switch mode power supplies (smps) with minimal external components. compared with discrete mosfet and pwm controller solution, it can reduce total cost, component count, size and weight, while simulta neously increasing efficiency, productivity, and system reliability. figure 1 shows the basic schematic of an fps based quasi- resonant converter for the color tv application, which also serves as the reference circ uit for the design process described in this application note. an experimental converter from the design example has b een built and tested to show the validity of the design procedure. figure 1. basic quasi-resonant converte r (qrc) using fps (color tv application) vcc gnd drain sync pwm v fb ac in fscq-series n s2 d r2 c o2 ka431 h11a817a r d r bias r 1 r 2 r f c f l p2 c p2 v o1 (b+) v o2 (sound) d r1 l p1 c o1 c p1 linear regulator mcu picture on r 3 r 1 q n a n p n s1 cr d sy r sy1 r sy2 c sy c b r cc c a1 c a2 d r(n) l p(n) c o(n) c p(n) n s(n) v o(n) d a d zc r str vco dz
AN4146 application note 2 ?2005 fairchild semiconductor corporation 2. step-by-step design procedure figure 2. flow chart of design procedure in this section, a design procedure is presented using the schematic of figure 1 as a refere nce. figure 2 illustrates the design flow chart. the detail ed design procedures are as follows: [step-1] define the system specifications - line voltage range ( v line min and v line max ). - line frequency ( f l ). - maximum output power ( p o ). - estimated efficiency ( e ff ) : the power conversion efficiency must be estimated to calculate the maximum input power. if no reference data is available, set e ff = 0.7~0.75 for low voltage output applications and e ff = 0.8~0.85 for high voltage output applications. in the case of color tv applications, the typical efficiency is 80~83%. with the estimated efficiency, the maximum input power is given by for multiple output smps, the load occupying factor for each output is defined as where p o(n) is the maximum output power for the n-th output. for single output smps, k l(1) =1. it is assumed that v o1 is the reference output that is regulated by the feedback control in normal operation. [step-2] determine dc link capacitor (c dc ) and the dc link voltage range. typically, the dc link capacitor is selected as 2-3uf per watt of input power for universal input range (85-265vrms) and 1uf per watt of input power for european input range (195v- 265vrms). with the dc link capacitor selected, the minimum dc link voltage is obtained as where c dc is the dc link capacitor and d ch is the duty cycle ratio for c dc to be charged as defined in figure 3, which is typically about 0.2. p in , v line min and f l are specified in step-1. the maximum dc link voltage is given as where v line max is specified in step-1. 1. define the system specifications (v line min , v line max , f l , p o , e ff ) 2. determine dc link capacitor (c dc ) and dc link voltage range 3. determine the reflected output voltage (v ro ) 6. determine the proper core and the minimum primary turns (n p min ) 7. determine the number of turns for each output and vcc auxiliary circuit 5. choose proper fps considering input power and i ds peak 4. determine the transformer primary side inductance (l m ) is the winding window area (aw) enough ? y n is it possible to change the core ? y n 8. determine the startup resistor 9. determine the wire diameter for each winding 13. design the voltage drop circuit for burst operation design finished 14. design the feedback control circuit 12. design the synchronization network 11. determine the output capacitors 10. choose the secondary side rectifier diodes p in p o e ff ------ - = (1) k ln () p on () p o ------------- = (2) v dc min 2 v line min () ? 2 p in 1d ch ? () ? c dc f l ? ------------------------------------ ? = (3) v dc max 2v line max = (4)
application note AN4146 3 ?2005 fairchild semiconductor corporation figure 3. dc link voltage waveform [step-3] determine the reflected output voltage (v ro ) figure 4 shows the typical waveforms of the drain voltage of quasi-resonant flyback conv erter. when the mosfet is turned off, the dc link voltage ( v dc ) together with the output voltage reflected to the primary ( v ro ) is imposed on the mosfet and the maximum nominal voltage across the mosfet ( v ds nom ) is where v dc max is as specified in eq uation (4). by increasing v ro , the capacitive switching loss and conduction loss of the mosfet are reduced. however, this increases the voltage stress on the mosfet as shown in figure 4. therefore, v ro should be determined by a trade-off between the voltage margin of the mosfet and the ef ficiency. it is typical to set v ro as 120~180v so that v ds norm is 490~550v (75~85% of mosfet rated voltage). figure 4. the typical waveform of mosfet drain voltage for quasi resonant converter [step-4] determine the transformer primary side inductance (l m ) figure 5 shows the typical waveforms of mosfet drain current, secondary diode cu rrent and the mosfet drain voltage of a quasi-resonant converter. during t off , the current flows through the second ary side rectifier diode and the mosfet drain volt age is clamped at ( v dc + v ro ). when the secondary side current redu ces to zero, the drain voltage begins to drop because of the resonance between the effective output capacitor of the mosfet and the primary side inductance ( l m ). to minimize the switching loss, the fscq-series is designed to turn on the mosfet when the drain voltage reaches its minimum voltage ( v dc - v ro ). figure 5. typical waveforms of quasi-resonant converter to determine the primary side inductance (l m ), the following variables should be determined beforehand. ? the minimum switching frequency ( f s min ) : the minimum switching frequency occurs at the minimum input voltage and full load condition, which should be higher than the minimum switching frequency of fps (20khz). by increasing f s min , the transformer size can be reduced. however, this resu lts in increased switching losses. therefore determine f s min by a trade-off between switching losses and transformer size. typically, f s min is set to be around 25khz. ? the falling time of the mosfet drain voltage ( t f ) : as shown in figure 5, the mosfet drain voltage fall time is half of the resonant period of the mosfet?s effective output capacitance an d primary side inductance. by increasing t f , emi can be reduced. meanwhile, this forces an increase of the resonant capacitor ( cr ) resulting in increased switching losse s. the typical value for t f is 2-2.5us. dc link voltage minimum dc link voltage t 1 t 2 d ch = t 1 / t 2 = 0.2 v ds nom v dc max v ro + = (5) - v ro + + v dc - drain gnd fps + v ds - 0 v v dc max v ro v ro v ds nom l m c r + v o - v ro v ro v ds nom v dc v ro v ro v ds i ds t f t off t on t s i d v dc +v ro v dc -v ro
AN4146 application note 4 ?2005 fairchild semiconductor corporation after determining f s min and t f , the maximum duty cycle is calculated as where v dc min is specified in equation (3) and v ro is determined in step-3. then, the primary side inductance is obtained as where p in , v dc min and d max are specified in equations (1), (3), and (6), respectively and f s min is the minimum switching frequency. once l m is determined, the maximum peak current and rms current of the mosfet in norma l operation are obtained as where v dc min , d max and l m are specified in equations (3), (6) and (7), re spectively and f s min is the minimum switching frequency. [step-5] choose the proper fps considering input power and peak drain current. with the resulting maximum peak drain current of the mosfet ( i ds peak ) from equation (8), ch oose the proper fps whose the pulse-by-pulse current limit level ( i lim ) is higher than i ds peak . since fps has 12% tolerance of i lim , there should be some margin for i lim when choosing the proper fps device. table 1 shows the lineups of fscq-series with rated output power and pulse-by-pulse current limit. table 1. fps lineups with rated output power [step-6] determin e the proper core and the minimum primary turns. table 2 shows the commonly used cores for c-tv application for different output powers. when designing the transformer, consider the maximum flux density swing in normal operation ( ? b ) as well as the maximum flux density in transient ( b max ). the the maximum flux density swing in normal operation is related to the hysteresis loss in the core while the maximum flux density in transient is related to the core saturation. with the chosen core, the minimum number of turns for the transformer primary side to avoid the over temperature in the core is given by where l m is specified in equation (7), i ds peak is the peak drain current specified in equation (8), a e is the cross- sectional area of the transformer core in mm 2 as shown in figure 6 and ? b is the maximum flux density swing in tesla. if there is no reference data, use ? b =0.25~0.30 t. since the mosfet drain current exceeds i ds peak and reaches i lim in a transient or fault condition, the transformer should be designed not to be saturated when the mosfet drain current reaches i lim . therefore, the maximum flux density ( b max ) when drain current reaches i lim should be also considered as where l m is specified in equation (7), i lm is the pulse-by- pulse current limit, a e is the cross-secti onal area of the core in mm 2 as shown in figure 6 and b max is the maximum flux density in tesla. figure 7 sh ows the typical characteristics of ferrite core from tdk (pc40). since the core is saturated at low flux density as the temper ature goes high, consider the high temperature characteristics. if there is no reference data, use b max =0.35~0.4 t. the primary turns should be determined as less than n p min values obtained from equation (10) and (11). figure 6. window area and cross sectional area maximum output power product 230vac 15% 85-265vac i lim (a) min typ max fscq0565rt 70 w 60 w 3.08 3.5 3.92 fscq0765rt 100 w 85 w 4.4 5 5.6 fscq0965rt 130 w 110 w 5.28 6 7.84 fscq1265rt 170 w 140 w 6.16 7 7.84 fscq1465rt 190 w 160 w 7.04 8 8.96 fscq1565rt 210 w 170 w 7.04 8 8.96 fscq1565rp 250 w 210 w 10.12 11.5 12.88 d max v ro v ro v dc min + ------------------------------------- 1 f s min t f ? () ? = (6) l m v dc min d max ? () 2 2f s min p in ?? --------------------------------------------- - = (7) i ds peak v dc min d max l m f s min ----------------------------------- = (8) i ds rms d max 3 ------------- - i ds peak ? =9 () n p min l m i ds peak ? ba e ------------------------- - 10 6 = (10) n p min l m i lim b max a e -------------------- 10 6 = (11) aw (mm 2 ) ae (mm 2 )
application note AN4146 5 ?2005 fairchild semiconductor corporation figure 7. typical b-h characteristics of ferrite core (tdk/pc40) table 2. commonly used cores for c-tv applications [step-7] determine the number of turns for each output and vcc auxiliary circuit figure 8 shows the simplified diagram of the transformer. it is assumed that v o1 is the reference output that is regulated by the feedback control in nor mal operation. it is also assumed that linear regulator is connected to v o2 to supply a stable voltage for mcu. first, calculate the turns ra tio (n) between the primary winding and reference output (v o1 ) winding as a reference as in where v ro is determined in step-3 and v o1 is the reference output voltage and v f1 is the forward voltage drop of diode ( d r1 ). then, determine the appropriate integer for n s1 so that the resulting n p is larger than n p min as where n is obtained in equation (12) and n p and n s1 are the number of turns for the primary side and the reference output, respectively. the number of turns for the other output (n-th output) is determined as where v o(n) is the output voltage and v f(n) is the diode ( d r(n) ) forward voltage drop of the n-th output, respectively. figure 8. simplified di agram of the transformer - vcc winding design : as shown in figure 9, fscq-series drops all the outputs including the vcc auxiliary voltage ( v a ) in standby mode to minimize the power consumption. because the vcc auxiliary voltage ( v a ) changes a over wide range, a regulation circuit usin g zener diode is typically used to provide a stable supply voltage (vcc) for fps in normal operation, as shown in figure 8. it is typical to design the regulation circuit so that the vcc voltage is regulated as 18v in normal operation and is above vcc stop voltage (9v) by 2~3v in standby operation as shown in figure 9. after fscq-series enters into standby mode, the current consumed by fps drops below 500ua and the voltage drop across r cc is negligible. output power core 70-100w eer35 100-150w eer40 eer42 150-200w eer49 100 500 400 300 200 800 1600 0 0 magnetic field h (a/m) flux density b (mt) magnetization curves (typical) material :pc40 100 60 25 n v r0 v o1 v f1 + ------------------------- - = (12) n p nn s1 n p min > ? = (13) n sn () v on () v fn () + v o1 v f1 + --------------------------------- =n s1 ? 14 () np n s1 - v ro + d r1 n a d a n s2 d r2 v o2 + - + v o1 - + v f2 - + v f1 - - v fa + v a + - n s(n) d r(n) + v o(n) - + v f(n) - linear regulator v cc + - 18v rcc
AN4146 application note 6 ?2005 fairchild semiconductor corporation figure 9. output voltage drop in standby mode in standby mode, v o2 is regulated by the feedback control and the voltage drop ratio of the v o2 winding is defined in where v f2 is the diode forward voltage drop of the d r2 , and v o2 normal and v o2 stby are the output voltages of v o2 in normal mode and standby mode, respectively, as shown in figure 9. assuming that the vcc auxiliary voltage ( v a ) is reduced with the ratio of k drop , v a in normal mode is obtained as where v a stby is the minimum voltage of v a in standby mode, which should be larger than vcc stop voltage of fps (typically 9v). notice that the operating current is reduced in standby mode and therefore the voltage drop across r cc is negligible. it is typical to have a voltage margin of 2-3v when determining v a stby . after determining v a normal , the number of turns for the vcc auxiliary winding ( n a ) is obtained as where v fa is the forward voltage drop of d a as defined in figure 8. - vcc drop resistor (r cc ) : the current consumed by fps in normal operation is given by where i op and i drv are the currents required for ic operation and mosfet gate drive, respectively. i op is given in the data sheet and i drv is obtained as where c iss is the input capacitance of the mosfet and f s is the switching frequency. when considering i drv , it is typical to assume that v cc is vz (18v) and f s is 90khz. the condition for the vcc drop resistor (r cc ) is given by the heat dissipation of r cc in normal operation is given by where v z is the zener breakdown voltage (typically 18v). when a large voltage drop of more than 20v is required, application circuit shown in figure 11 is preferred to minimize the power dissipation in the voltage drop circuit. figure. 10 vcc auxiliary circuit for a large voltage drop [step-8] determine the startup resistor figure 10 shows the typical circuit of vcc winding for fscq-series. initially, fps c onsumes only startup current (max 50ua) before it begins switching. therefore, the current supplied through the startup resistor ( r str ) can charge the capacitors c a1 and c a2 while supplying startup current to fps. when vcc reaches start voltage of 15v (v start ), fps begins switching and the current consumed by fps increases. then, the current re quired by fps is supplied from the transformer?s auxiliary winding. v o2 v o2 stby v a 9v standby mode normal mode v a stby v o2 normal v a normal 18v v cc 2-3 v k drop v 02 stby v f2 + v 02 normal v f2 + ------------------------------------------ = (15) v a normal v a stby v fa + k drop -------------------------------- -v f2 ? =16 () n a v a normal v fa + v o1 v f1 + --------------------------------------- =n s1 ? 17 () i cc i op i drv + =18 () i drv v cc c iss f s ?? = 19 () r cc v co normal v z ? i cc ------------------------------------- - <20 () p a v co normal v z ? () 2 r cc -------------------------------------------- - = 21 () fscq-series v cc d a c a1 vz (18v) 10k ? 3-5 ? c a2
application note AN4146 7 ?2005 fairchild semiconductor corporation figure. 11 startup and vcc auxiliary circuit - startup resistor (r str ) : the average of the minimum current supplied through the startup resistor is given by where v line min is the minimum input voltage, v start is the start voltage (15v) of fps and r str is the startup resistor. the startup resistor should be chosen so that i sup avg is larger than the maximum startup current ( 50ua). if not, vcc can not be charged up to the start voltage and fps will fail to start up. the maximum startup time is determined as where c e is the effective vcc capacitor ( c a1 +c a2 ) and i start max is the maximum startup current (50ua) of fps. once the startup resistor ( r str ) is determined, the maximum approximate power dissipation in r str is obtained as where v line max is the maximum input voltage, which is specified in step-1. the startup resistor should have a proper dissipation rating based on the value of p str . [step-9] determine the wire diameter for each winding based on the rms current of each output. the rms current of the n-th secondary winding is obtained as where d max and i ds rms are specified in eq uations (6) and (9), v o(n) is the output voltage of the n-th output, v f(n) is the diode ( d r(n) ) forward voltage drop, v ro is specified in step-3 and k l(n) is the load occupying factor for n-th output defined in equation (2). the current density is typically 5a/mm 2 when the wire is long (>1m). when the wire is short with a small number of turns, a current density of 6-10 a/mm 2 is also acceptable. avoid using wire with a diamet er larger than 1 mm to avoid severe eddy current losses as well as to make winding easier. for high current output, it is recommended using parallel windings with multiple strands of thinner wire to minimize skin effect. check if the winding wi ndow area of the core, a w (refer to figure 6) is enough to accomm odate the wires. the required winding window area ( a wr ) is given by where a c is the actual conductor area and k f is the fill factor. typically the fill factor is 0.2~0.25 for single output applications and 0.15~0.2 for multiple outputs applications. if the required window ( a wr ) is larger than the actual window area ( a w ), go back to th e step-6 and change the core to a bigger one. sometimes it is impossible to change the core due to cost or size constrai nts. in that case, reduce v ro in step-3 or increase f s min , which reduces the primary side inductance ( l m ) and the minimum number of turns for the primary ( n p min ) shown in equation (7) and (10). [step-10] choose the proper rectifier diodes in the secondary side based on the voltage and current ratings. the maximum reverse voltage and the rms current of the rectifier diode ( d r(n) ) of the n-th output are obtained as where k l(n) , v dc max , d max and i ds rms are specified in equations (2), (4), (6) and (9), respectively, v ro is specified in step-3, v o(n ) is the output voltage of the n-th output and v f(n) is the diode ( d r(n) ) forward voltage drop. the typical fscq-series rstr vcc c a1 da i sup ac line c dc c a2 vco r cc vz (18v) i sup avg 2v line min ? ------------------------------------- v start 2 ----------------- ? ?? ?? ?? ?? 1 r str ----------- - ? = 22 () t str max c e v start i sup avg i start max ? () --------------------------------------------------- ? = 23 () p str 1 r str ----------- - v line max ?? ?? 2 v start 2 + 2 --------------------------------------------------------------- - 22 v start v line max ?? ----------------------------------------------------------------- ? ?? ?? ?? ?? ?? ? = 24 () i n () sec rms i ds rms 1d max ? d max ---------------------- - v ro k ln () ? v on () v fn () + () -------------------------------------- ? =25 () a w r a c k f ? = (26) v dn () v on () v dc max v on () v fn () + () ? v ro --------------------------------------------------------------- - + =27 () i dn () rms i ds rms 1d max ? d max ---------------------- - v ro k ln () v on () v fn () + () -------------------------------------- ? =28 ()
AN4146 application note 8 ?2005 fairchild semiconductor corporation voltage and current margins for the rectifier diode are as follows where v rrm is the maximum reverse voltage and i f is the average forward curr ent of the diode. a quick selection guide for the fairchild semiconductor rectifier diodes is given in table 3. in this table, t rr is the maximum reverse recovery time. table 3. fairchild diode quick selection table [step-11] determine the output capacitors considering the voltage and current ripple. the ripple current of th e n-th output capacitor ( c o(n) ) is obtained as where i o(n) is the load current of the n-th output and i d(n) rms is specified in equation (28) . the ripple current should be smaller than the maximum rippl e current specification of the capacitor. the voltage ripple on the n-th output is given by where c o(n) is the capacitance, r c(n) is the effective series resistance (esr) of the n-th output capacitor, k l(n) , d max and i ds peak are specified in equations (2), (6) and (8) respectively, v ro is specified in step-3, i o(n) and v o(n) are the load current and output voltage of the n-th output, respectively and v f(n) is the diode ( d r(n) ) forward voltage drop. sometimes it is impossible to meet the ripple specification with a single output capacitor due to the high esr of the electrolytic capacitor. in those cases, use additional lc filter stages (post filter) to reduce the ripple on the output. [step-12] design the synchronization network. the fscq-series employs a quasi-resonant switching technique to minimize the switching noise and loss. in this technique, a capacitor ( c r ) is added between the mosfet drain and source as shown in figure 12. the basic waveforms of a quasi-resonant converter are shown in figure 13. the external capacito r lowers the rising slope of drain voltage, which reduces the emi caused by the mosfet turn-off. to minimize the mosfet switching loss, the mosfet should be turned on when the drain voltage reaches its minimum value as shown in figure 13. the optimum mosfet turn-on time is indirectly detected by monitoring the vcc winding voltage as shown in figure 12 and 13. the output of the sync detect co mparator (co) becomes high when the sync voltage ( v sync ) exceeds 4.6v and low when the v sync reduces below 2.6v. the mosfet is turned on at the falling edge of the sync detect comparator output (co). ultra fast recovery diode products v rrm i f t rr package egp10b 100 v 1 a 50 ns do-41 uf4002 100 v 1 a 50 ns do-41 egp20b 100 v 2 a 50 ns do-15 egp30b 100 v 3 a 50 ns do-210ad fes16bt 100 v 16 a 35 ns to-220ac egp10c 150 v 1 a 50 ns do-41 egp20c 150 v 2 a 50 ns do-15 egp30c 150 v 3 a 50 ns do-210ad fes16ct 150 v 16 a 35 ns to-220ac egp10d 200 v 1 a 50 ns do-41 uf4003 200 v 1 a 50 ns do-41 egp20d 200 v 2 a 50 ns do-15 egp30d 200 v 3 a 50 ns do-210ad fes16dt 200 v 16 a 35 ns to-220ac egp10f 300 v 1 a 50 ns do-41 egp20f 300 v 2 a 50 ns do-15 egp30f 300 v 3 a 50 ns do-210ad egp10g 400 v 1 a 50 ns do-41 uf4004 400 v 1 a 50 ns do-41 egp20g 400 v 2 a 50 ns do-15 egp30g 400 v 3 a 50 ns do-210ad uf4005 600 v 1 a 75 ns do-41 egp10j 600 v 1a 75 ns do-41 egp20j 600 v 2 a 75ns do-15 egp30j 600 v 3 a 75 ns do-210ad uf4006 800 v 1 a 75 ns to-41 uf4007 1000 v 1 a 75 ns to-41 v rrm 1.3 v dn () ? > (29) i f 1.5 i dn () rms ? > (30) i cap n () rms i dn () rms () 2 i on () 2 ? = (31) ? v on () i on () d max c on () f s min -------------------------- i ds peak v ro r cn () k ln () v on () v fn () + () ----------------------------------------------------------- ( 3 2 ) + =
application note AN4146 9 ?2005 fairchild semiconductor corporation figure. 12 synchronization circuit the peak value of the sync signal is determined by the voltage divider network r sy1 and r sy2 as where v a normal is the vcc auxiliary voltage in normal mode. choose the voltage divider r sy1 and r sy2 so that the peak value of sync voltage ( v sync pk ) is lower than the ovp threshold voltage (12v) to avoid triggering ovp in normal operation. it is typical to set v sync pk to be 8~10v. to synchronize the v sync with the mosfet drain voltage, the sync capacitor ( c sy ) should be chosen so that t f is same as t q as shown in figure 13. t f and t q are given as where l m is the primary side inductance of the transformer, n s and n a are the number of turns for the output winding and vcc winding, respectively, v a normal is the vcc auxiliary voltage in normal mode and c eo is the effective mosfet output capacitance ( c oss + c r ). figure. 13 synchronization waveforms [step-13] design voltage drop circuit for the burst operation. figure 14. typical feedback circuit to drop output voltage in standby mode to minimize the power consumption in the standby mode, fscq-series employs burst oper ation. once fps enters into burst mode, all output voltag es and effective switching frequencies are reduced. figure 14 shows the typical output voltage drop circuit for c-tv applications. under normal vcc c a1 d a c a2 gnd c r drain i ds r cc r sy1 r sy2 sync v o1 c sy + v ds - n s1 n p l m + - co 4.6/2.6v 18v vco d sy n a fscq-series v sync sync comparator v sync pk r sy2 r sy1 r sy2 + ---------------------------------- v a normal ? = 33 () t f l m c eo ? ? = (34) t q r sy2 c sy v a normal 2.6 ------------------- - r sy2 r sy1 r sy2 + ---------------------------------- ? ?? ?? ?? ln ?? = (35) v dc v ro v ro v ds t f 4.6v v sync t q 2.6v v sync pk co mosfet gate on on v ovp (12v) picture on micom linear regulator v o2 v o1 (b+) ka431 r 2 r 1 r 3 r bias r d r f c f d 1 q1 a c r dz (v zb )
AN4146 application note 10 ?2005 fairchild semiconductor corporation operation, the picture on signal is applied and the transistor q 1 is turned on, which de-couples r 3 , d z and d 1 from the feedback network. thus, only v o1 is regulated by the feedback circuit in normal operation and is determined as figure 15 shows the standby mode operation waveforms. in standby mode, the picture on signal is disabled and the transistor q 1 is turned off, which couples r 3 , d z and d 1 to the reference pin of ka431. if r 3 is much smaller than r 1 , v o2 is dominant in the feedback loop. before v o2 drops to v o2 stby , the voltage on the reference pin of ka431 is higher than 2.5v, which increases th e current through the opto led. this pulls down the feedback voltage ( v fb ) of fps and forces to stop switching. once fps stops switching, v o2 decrease, and when v o2 reaches v o2 stby , the current through the opto led decreases allowi ng the feedback voltage to rise. when the feedback volta ge reaches 0.4v, fps resumes switching with a predeter mined peak drain current. assuming that the forward voltage drop of d 1 is 0.5v, the approximate output voltage for v o2 in standby mode is given by where v zb is the zener breakdown voltage of d z . figure 15. burst operation waveforms [step-14] design the feedback control circuit. since fscq-series employs curre nt mode control as shown in figure 16, the feedback lo op can be easily implemented with a one-pole and one-zero compensation circuit. the current control factor of fps, k is defined as where i pk is the peak drain current and v fb is the feedback voltage for a given operating condition, i lim is the current limit of the fps and v fbsat is the internal feedback saturation voltage, which is typically 2.5v. figure 16. control block diagram for quasi-resonant flyback converter, the control-to-output transfer function using current mode control is given by where v d c is the dc input voltage, r l is the effective total load resistance of the controll ed output, which is defined as v o1 2 /p o , n p and n s1 are specified in step-7, v ro is specified in step-3, v o1 is the reference output voltage, p o is specified in step-1 and k is specified in equation (38). the pole and zeros of equation (39) are defined as where l m is specified in equation (7), d is the duty cycle of v o1 2.5 r 1 r 2 + r 2 -------------------- ?? ?? ? = (36) v 02 stby v zb 0.5 2.5 ++ = (37) v o2 v o2 stby v fb 0.4v standby mode normal mode i ds k i pk v fb ---------- i lim v fbsat ----------------- = = (38) . ? ? 1 o fb v and v in order to express the small signal ac transfer functions, the small signal variations of feedback voltage ( v fb ) and controlled output voltage ( v o1 ) are introduced as v o1 r d i d r bias r 1 r 2 i bias c b v fb ctr :1 fps v bias c f r f ka431 i pk mosfet current r b g vc v ? o1 v ? fb --------- = kr l v dc n p n s1 ? () ? 22v ro v dc + () ----------------------------------------------------- 1s +w z ? () 1s ? w rz ? () 1s +w p ? ---------------------------------------------------------- ? =39 () w z 1 r c1 c o1 ------------------- -, w rz r l 1d ? () 2 dl m n s1 n p ? () 2 ---------------------------------------- - and w p 1d + () r l c o1 ------------------ - == =
application note AN4146 11 ?2005 fairchild semiconductor corporation the fps, c o1 is the output capacitor of v o1 and r c1 is the esr of c o1 . when the converter has more than one output, the low frequency control-to-output tran sfer function is proportional to the parallel combination of all load resistance, adjusted by the square of the turns ratio. therefore, the effective load resistance is used in equation (39) instead of the actual load resistance of v o1 . notice that there is a right half plane (rhp) zero ( w rz ) in the control-to-output transfer function of equation (39). because the rhp zero reduces the phase by 90 degrees, the crossover frequency should be placed below the rhp zero. figure 17 shows the variation of a quasi-resonant flyback converter control-to-output transfer function for different input voltages. this figure shows the system poles and zeros together with the dc gain change for different input voltages. the gain is highest at the high input voltage condition and the rhp zero is lowest at the low input voltage condition. figure 18 shows the variation of a quasi-resonant flyback converter control-to-output transfer function for different loads. this figure shows that the gain between f p and f z does not change for different loads and the rhp zero is lowest at the full load condition. the feedback compensation ne twork transfer function of figure 16 is obtained as and r b is the internal feedback bi as resistor of fps, which is typically 2.8k ? , ctr is the current transfer ratio of opto coupler and r 1 , r d , r f , c f and c b are shown in figure 16. figure 17. qr flyback converter control to output transfer function variation for different input voltages figure 18. qr flyback converter contro to output transfer function variation for different loads when the input voltage and the load current vary over a wide range, determining the wors t case for the feedback loop design is difficult. the gain together with zeros and poles varies according to the operating conditions. one simple and practical solution to this problem is designing the feedback loop for low input voltage and full load condition with enough phase and gain margin. the rhp zero is lowest at low input voltage and full load condition. the gain increases only about 6db as the operating condition is changed from the lowest input voltage to the highest input voltage condition under universal input condition. the procedure to design the feedback loop is as follows (a) set the crossover frequency ( f c ) below 1/3 of rhp zero to minimize the effect of the rhp zero. set the crossover frequency below half of the minimum switching frequency ( f s min ). (b) determine the dc gain of the compensator ( w i /w zc ) to cancel the control-to -output gain at f c . (c) place a compensator zero ( f zc ) around f c /3 . (d) place a compensator pole ( f pc ) around 3 f c . figure 19. compensator design v fb ? v o1 ? --------- - w i s ----- 1sw zc ? + 1sw pc ? + -------------------------- ? =40 () where w i r b ctr ? r 1 r d c f ------------------------ - , w zc 1 r f c f -------------- - , w pc 1 r b c b --------------- = = = 0 db 20 db -20 db -40 db 40 db 10hz 100hz 10khz 1khz 1hz 100kh z low input voltage high input voltage f p f p f z f z f rz f rz 0 db 20 db -20 db -40 db 40 db 10hz 100hz 10khz 1khz 1hz 100kh z heavy load li ght load f p f p f z f rz f rz 0 db 20 db -20 db -40 db 40 db 10hz 100hz 10khz 1khz 1hz 100khz control to output f p f z f rz compensator loop gain t f zc f pc f c
AN4146 application note 12 ?2005 fairchild semiconductor corporation when determining the feedback circuit component, there are some restrictions as described below: (a) design the voltage divider network of r 1 and r 2 to provide 2.5v to the reference pin of the ka431. the relationship between r 1 and r 2 is given as where v o1 is the reference output voltage. (b) the capacitor connect ed to feedback pin ( c b ) is related to the shutdown delay time in an overload condition by where v sd is the shutdown feedback voltage and i delay is the shutdown delay current. typical values for v sd and i delay are 7.5v and 5ua, respectivel y. in general, a 20 ~ 50 ms delay is typical for most applications. because c b also determines the high frequency pole ( w pc ) of the compensator transfer function as shown in equation (40), too large a c b can limit the control bandwidth by placing w pc at too low a frequency. typical value for c b is 10-50nf. (c) the resistors r bias and r d used together with the opto- coupler h11a817a and the shunt regulator ka431 should be designed to provide proper operating current for the ka431 and to guarantee the full swing of the feedback volt- age for the fps device chosen. in general, the minimum cathode voltage and current for the ka431 are 2.5v and 1ma, respectively. therefore, r bias and r d should be designed to satisfy the following conditions. where v bias is the ka431 bias voltage as shown in figure 16 and v op is opto-diode forward voltage drop, which is typically 1v. i fb is the feedback current of fps, which is typically 1ma. r 2 2.5 r 1 ? v o1 2.5 ? ----------------------- - = (41) t delay v sd 2.5 ? () =c b ? i delay ? (42) v bias v op ? 2.5 ? r d --------------------------------------------- i fb >43 () v op r bias ------------- -1ma > (44)
application note AN4146 13 ?2005 fairchild semiconductor corporation 3. design example usin g fps design assistant - it is assumed that the efficiency is 83% at the minimum input voltage and full load condition. - since the maximum input power is 101.2w, the dc link capacitor is set to be 220uf by 2uf/watt. - v ro is set to be 126v so that v ds nom should be about 77% of bv dss application device input voltag e output power output voltage (rated current) ripple spec color tv fscq0765rt 85-265vac (60hz) 83w 125v (0.4a) 24v (0.5a) 18v (0.5a) 12v (1.0a) 5% 5% 5% 5% fps design assistant for AN4146 ver 1.00 by h.s. choi blue cells are the input parameters red cells are the output parameters 1. define the system specifications minimum line voltage (v line min )85v.rms maximum line voltage (v line max ) 265 v.rms line frequency (f l )60hz v o(n) i o(n) p o(n) k l(n) 1st output (vo1) ; regulated by feedback 125 v 0.40 a 50 w60 % 2nd output (vo2) 24 v 0.50 a 12 w14 % 3rd output (vo3) 18 v 0.50 a 9 w11 % 4th output (vo4) 12 v 1.00 a 12 w14 % 5th output (vo5) v a 0 w0 % maximum output power (p o ) = 83.0 w estimated efficiency (e ff )82% maximum input power (p in ) = 101.2 w 2. determine dc link capacit or and dc link voltage range dc link capacitor (c dc ) 220 uf minimum dc link voltage (v dc min ) = 91 v maximum dc link voltage (v dc max )= 375 v 3. determine the reflected output (v ro ) output voltage reflected to primary (v ro ) 126 v maximum nominal drain voltage (v ds nom ) = 501 v
AN4146 application note 14 ?2005 fairchild semiconductor corporation - considering the tolerance of 12%, fscq0765rt is chos en, whose pulse-by-pulse curren t limit is 5a (typical). - eer3540 core is chosen, whose cross sectional area is 109mm 2 . 4. determine transformer primary side inductance (lm) drain voltage falling time (t f )2.3us minimum switching frequency of fps (f s_min )24khz maximum duty cycle (d max ) = 0.55 primary side inductance (l m ) = 514 uh maximum peak drain current (i ds peak ) = 4.05 a rms drain current (i ds rms ) = 1.73 a 5. choose the proper fps considering the input power and curren t limit typical current limit of fps (i lim )5.00a minimum i lim considering tolerance 4.40 a >a ->o.k. 4.05 6. determine the proper core and the minimum primary turns maximum flux density swing in normal mode ( ?
application note AN4146 15 ?2005 fairchild semiconductor corporation - in standby mode, v o2 is reduced from 24v to 8v. in order to prevent vcc under voltage lockout in standby mode, v a in standby mode is designed as 13v. then, v a would be 37.7v in normal mode. -assuming that the maximum switching frequency is 90khz, th e maximum current consumed by fps is 9ma. vcc resistor is determined as 1.5k ? . - for each winding, the diameter of wire is determined so that the cu rrent density shoul d be about 5a/mm 2 - for eer3540 core, the winding window area is 223mm 2 . assuming a fill factor of 0.2, this core is enough to accommodate the wires. maximum operating current of fps (i op )6ma mosfet input capacitance (c iss )1840pf breakdown voltage of vcc zener diode 18 v current consummed by fps (icc) = 9.0 ma at 90 khz vcc drop resistor (rcc) 1.5 k? <2 k? power dissipation of rcc = 0.3 w 8. determine the startup resistor maximum startup current of fps (i start )50ua startup resistor 240 k? <616 k? effective vcc capacitor (ce) 20 uf maximum dissipation in startup resistor = 0.13 w at 265 vac maximum startup time (t str max ) = 3.83 s at 85 vac 9. determine the wire di ameter for each winding diameter parallel i d(n) rms (a/mm 2 ) primary winding 0.6 mm 1 1.7 a6.1 winding for vcc (37.7v) 0.3 mm 1 0.1 a1.4 winding for vo1 (125v / 0.4a) 0.5 mm 1 0.9 a4.8 winding for vo2 (24v / 0.5a) 0.4 mm 2 1.1 a4.5 winding for vo3 (18v / 0.5a) 0.4 mm 2 1.1 a4.5 winding for vo4 (12v / 1a) 0.5 mm 2 2.2 a5.5 winding for vo5 (v / a) mm ##### a #### copper area (a c ) = 40.56 mm 2 fill factor (k f )0.2 required window area (a wr ) 202.78 mm 2
AN4146 application note 16 ?2005 fairchild semiconductor corporation - since the output capacitan ce of mosfet is 100pf (typical), exte rnal capacitor (cr) of 1nf is used. - zener diode with a breakdown voltage of 5.1v is chosen. vcc winding 1n4937 ultra fast recovery vo1 (125v) egp20j (600v/2 a) ultra fast recovery vo2 (24v) egp20d (200v/2a) ultra fast recovery vo3 (18v) egp20d (200v/2a) ultra fast recovery vo4 (12v) egp20d (200v/2a) ultra fast recovery 10. choose the rectifier diode in the secondary side v d(n) i d(n) rms rectifier diode for vcc 153 v0.10 a rectifier diode for vo1 (125v / 0.4a) 500 v0.95 a rectifier diode for vo2 (24v / 0.5a) 99 v1.14 a rectifier diode for vo3 (18v /0.5a) 75 v1.12 a rectifier diode for vo1 (12v /1a) 51 v2.17 a rectifier diode for vo5 (v /a) 0 v ##### a 11. determine the output capacitor c o(n) r c(n) i cap(n) v o(n) output capacitor for vo1 (125v / 0.4a) 100 uf 100 m? 0.9 a0.3 v output capacitor for vo2 (24v / 0.5a) 1000 uf 100 m? 1.0 a0.3 v output capacitor for vo3 (18v / 0.5a) 1000 uf 100 m? 1.0 a0.3 v output capacitor for vo4 (12v / 1a) 1000 uf 100 m? 1.9 a0.6 v output capacitor for vo5 (v / a) uf m? ##### a #### v 12. design the synchronization network peak value of sync voltage (v sync pk )9.0v 4.6 < v sync pk < 12v (v ovp ) sync voltage divider resistor (r sy1 )1500? sync voltage divider resistor (r sy2 ) 470 ? effective output capacitance of mosfet 1.0 nf ( coss + cr ) sync capacitor (c sy )3.9nf 13. design voltage drop circuit for the burst operation vo2 in standby mode (v o2 stby ) 8.0 v breakdown voltage of zener diode, dz 5.0 v
application note AN4146 17 ?2005 fairchild semiconductor corporation 14. design the feedback control circuit control-to-output dc gain = 50 control-to-output zero (w z ) = 100.0 krad/s => f z =hz control-to-output rhp zero (w rz )= 136.0 krad/s => f rz =hz control-to-output pole (w p )= 82 rad/s => f p =hz voltage divider resistor (r 1 )100? voltage divider resistor (r 2 )= 2.0 ? opto coupler diode resistor (r d )1? ka431 bias resistor (r bias )1.2? feeback pin capacitor (c b ) = 47 nf feedback capacitor (c f ) = 22 nf feedback resistor (r f ) = 39 ? current transfer ratio of opto coupler (ctr) 100 % feedback integrator gain (w i ) = 1273 rad/s => f i =hz compensator zero (w zc )= 1166 rad/s => f zc =hz compensator pole (w pc )= 7599 rad/s => f pc = hz 203 186 1,210 15,924 21,650 13 v o1 r d i d r bias r 1 r 2 i bias c b v fb ctr:1 fps v o2 c f r f ka431 -60 -40 -20 0 20 40 60 80 100 1 10 100 1000 10000 frequency (hz) gain (db) control-to-output compens ator closed loop gain (t)
AN4146 application note 18 ?2005 fairchild semiconductor corporation - the control bandwidth (crossover frequency) is about 600hz with a phase margin of 50 degrees. -180 -150 -120 -90 -60 -30 0 1 10 100 1000 10000 frequency (hz) phase (degree) control-to-output compens ator closed loop gain (t)
application note AN4146 19 ?2005 fairchild semiconductor corporation design summary ? high efficiency (>80% at 85vac input) ? wider load range through the extended quasi-resonant operation ? low standby mode power consumption (<1w) ? low component count ? enhanced system reliability through various protection functions ? internal soft-start (20ms) key design notes ? 24v output is designed to drop to around 8v in standby mode ? zener diode zd102 is used for a safety test such as ul. when the drain pin and feedback pin are shorted, the zener diode fails and remains short, which causes the fuse (f1) to pop a nd prevents explosion of the op to-coupler (ic301). this zener diode also increases the im munity against line surge. 1. schematic figure 20. schematic of design example c104 10uf 50v 1 3 4 10 t1 eer3540 12v, 1a c204 1000uf 35v d205 egp20d 11 lf101 c101 330nf 275vac fuse 250v 3.0a c102 220uf 400v rt101 5d- 9 bd101 d103 1n4937 r103 5.1 ? 0.25w 6 7 r104 1.5k ? 0.25w 24 5 1 3 gnd drain sync fb vcc d106 1n4148 ic101 fscq0765rt c103 47nf 50v r105 470 ? 0.25w c105 3.9nf 50v zd101 18v 1w c107 1nf 1kv bead101 d105 1n4937 c210 470pf 1kv 18v, 0.5a d204 egp20d c205 1000uf 35v 13 c209 470pf 1kv 12 125v, 0.4a d202 egp20j c201 100uf 160v 14 c207 470pf 1kv l202 bead 16 c202 47uf 160v 24v, 0.5a d203 egp20d c203 1000uf 35v 17 c208 470pf 1kv 18 opt101 817a r201 1k ? 0.25w c206 22nf 50v c301 2.2nf q201 ka431lz r203 39k ? 0.25w r202 1k ? 0.25w r205 100k ? 0.25w r204 2.0k ? 0.25w vr201 30k ? d201 1n4148 q202 ksc945 r206 10k ? 0.25w r207 5.1k ? 0.25w sw 201 15 r102 120k ? 0.25w r101 120k ? 0.25w r106 1.5k ? 1w c106 10uf 50v zd201 5.1v 0.5w r208 1k ? 0.25w zd102 12v 1w
AN4146 application note 20 ?2005 fairchild semiconductor corporation 2. transformer specifications figure 21. transformer schematic diagram winding specification electrical characteristics core & bobbin core : eer 3540 bobbin : eer3540 ae : 109 mm 2 no pin (s f) wire turns winding method n p1 1 - 3 0.6 1 32 center winding n 125v/2 16 - 15 0.5 1 32 center winding n 24v 18 - 17 0.4 2 13 center winding n 12v 12 - 13 0.5 2 7 center winding n p2 3 - 4 0.6 1 32 center winding n 125v/2 15 - 14 0.5 1 32 center winding n 18v 11 - 10 0.4 2 10 center winding n a 7 - 6 0.3 1 20 center winding pin specification remarks inductance 1 - 3 514uh 5% 1khz, 1v leakage inductance 1 - 3 10uh max 2 nd all short eer 3540 n 24v n a 7 13 14 15 16 17 18 n 125v /2 n 12v n 18v n p1 n p2 1 2 3 4 5 6 8 910 11 12 n 125v /2 n 125v /2 n p2 n 12v n 125v /2 n 24v n p1 n 18v n a
application note AN4146 21 ?2005 fairchild semiconductor corporation experimental verification to show the validity of the design procedure presented in this application note, we have built and tested the converter in the design example. all the circuit components are used as designed in the design ex ample. the schematic and transformer specifications are shown in figure 20 and 21, respectively. the figure 22 shows the fps drain current and the dc link voltage waveforms at the minimum input voltage and full load condition. as shown, the minimum dc link voltage ( v dc min ) is about 90v, which is the same as the designed value in step-2 of page 13. figure 23 shows the fps drain current and voltage waveforms at the minimum input voltage and full load condition. as can be seen, th e maximum peak drain current ( i ds peak ) is about 3.9a and the minimum switching frequency ( f s min ) is 26khz. the values in the design are 4.05a for i ds peak and 24khz for f s min as can be seen in step-4 of page 14. figure 24 shows the fps drain current and voltage waveforms at the maximum input voltage and full load condition. as calculated in step-3 of page 13, the nominal drain voltage is about 500v. figures 25 and 26 show the waveforms of vsync, drain voltage and drain current at the maximum input voltage and full load condition. as designed, the mosfet drain fall time is 2.3us and the mosfet is turned on when the drain voltage reaches its minimum value. figure 27 shows the waveforms of vcc, drain voltage and drain current. the me asured startup time is 2.45s, which is smaller than the calculated maximum startup time of 3.83s in step-8 of page 15. when the typical value for the startup current (25us) is used for the equation (19), the typical startup time is calculated as figure 28 shows the output voltage drop in standby mode. as designed, the 24v output drops down to 8v. figure 29 shows the detailed burst mode operation waveforms. burst mode operation alternately enables and disables switching of the mosfet thereby reducing switching loss in standby mode. the table 4 shows the line regulation of each output. the figure 30 shows the measur ed efficiency at the full load condition for different input voltages. the minimum efficiency is about 81% at the minimum input voltage condition. figure 22. waveforms of drain current and dc link voltage at 85vac and full load condition (time:2ms/div) figure 23. waveforms of drain current and voltage at 85vac and full load condition (time : 10us/div) figure 24. waveforms of drain current and voltage at 265vac and full load condition (time : 5us/div) t str max c e v start i sup avg i start max ? () --------------------------------------------------- ? 2.91s ==
AN4146 application note 22 ?2005 fairchild semiconductor corporation figure 25. vsync, vds and ids waveforms at 265vac and full load condition (time : 5us/div) figure 26. vsync, vds and ids waveforms at 265vac and full load condition (time : 2us/div) figure 27. vcc, vds and ids waveforms at 265vac and full load condition (time : 2/div) figure 28. output voltage drop in the standby mode figure 29. burst mode operation table 4. line regulation of each output at full load condition input voltage v o1 (125v) v o2 (24) v o3 (18v) v o4 (12v) 85vac 125.3 v 24.25 v 18.88 v 12.85 v 110vac 125.3 v 24.23 v 18.87 v 12.84v 160vac 125.3 v 24.20 v 18.87 v 12.82 v 220vac 125.3v 24.19 v 18.85 v 12.81 v 265vac 125.3 v 24.18 v 18.85 v 12.79 v
application note AN4146 23 ?2005 fairchild semiconductor corporation figure 30. measured efficiency efficiency (%) 75 80 85 90 85 115 145 175 205 235 265 input voltage (vac)
AN4146 application note 9/20/05 0.0m 002 ? 2005 fairchild semiconductor corporation disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve re liability, function or design. fairchild does not assume any liability arising out of the applic ation or use of any product or circuit described herein; neither does it convey any license under its pat ent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corproation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose fa ilure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com by hang-seok choi / ph. d power conversion team / fairchild semiconductor phone : +82-32-680-1383 facsimile : +82-32-680-1317 e-mail : hangseok.choi@fairchildsemi.com

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